#7018 reads the low-half factors of v_mul_lo_u16 and v_pk_mul_lo_u16
as 24-bit fields because AMD's Windows driver stores the full 32-bit
product when it knows both factors fit in 16 bits. #7673's fold of
BitFieldUExtract(x, 0, n) into x removed those reads when the program
had masked the factors to 16 bits, so agc_driver_mul_lo_u16_high_half
failed again on that driver. The folder now keeps a field read that a
multiply uses.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
The constant folder now knows which bits a value can hold (masks, merges,
shifts, field extracts, 16- and 8-bit widenings, selects) and which bits a
user reads:
- a mask that clears no bit the value can hold is dropped, and so is a
merged part with no bit under the mask;
- And(And(x, a), m) becomes And(x, m) when m keeps no bit outside a, and a
mask rewrite is folded again;
- a field extract, shift, mask or 16-bit truncation reads through masks
that keep the bits it reads and through merged parts that hold none;
- a right shift of a left shift by the same amount becomes a mask;
- BitFieldUExtract(x, 0, n) is x when x has no bit at or above n;
- Or of two masked parts of one word becomes the word under the union of
the masks (the word itself when they cover it);
- a field extract of a left shift reads the unshifted word.
These patterns come from 16-bit halves of 32-bit registers (f16 and packed
math), which the translator splits and merges per instruction.
Test: agc_constant_bit_test gets six cases (repeated, narrower and wider
masks, a mask under a merge, half extractions, halves that rejoin); all six
fail on main.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01XBXM4pgkMHYEtqN1EQni2P
FoldVertexLaneBounds replaced every LaneId < 32 compare of a vertex
program on a fixed 32-lane host subgroup with true. The half-wave scan
matcher of the SPIR-V backend recognises a lane word by the select of its
low and high words on that compare. A scan keyed by the entry EXEC ballot
lost that shape, so its v_readlane_b32 of lane 63 was no longer read as a
half-wave reduction and the recompile failed (agc_shader_memory).
Fold the lane word select itself instead, and only when both words are
constants. Lane words built from ballots or other values keep their
lower-half test.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
A descriptor dword built by S_BREV_B32, V_BFREV_B32 or S_BREV_B64 from a
constant stayed a runtime value, so the resource could not be resolved
and the shader failed to prepare. The constant folder now reverses the
bits of an immediate the way the hardware does (D[31-i] = S0[i]), like
the existing BitCount32 fold. ConstantBitTest covers the fold.
Co-Authored-By: Claude Haiku 5.5 <noreply@anthropic.com>
A select of exec and zero gives a mask that is the same for every lane. Reading
it back went through a lane number, which Metal does not have in a vertex
shader, so MoltenVK rejected the shader. The select now stores the lane bit and
marks the pair as a mask, a constant mask word reads as a constant, and the
constant folder removes the bit test on an all-zero or all-one word.
agc_scalar_select_mask runs the translated IR over a wave and pins the lane
values for scc set and clear, a source that differs per lane, the two wave64
halves differing, a destination that is also a source, and constant and
literal sources.
Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
