Adrià FranchandClaude 03401459f9 perf(agc): pipelined draws and exact draw write ranges on by default ...

Queue 0 now pipelines draw commits unless APS5_PIPELINED_DRAWS=0, and draw write ranges use the exact
color, DCC, CMASK, depth and stencil sizes unless APS5_EXACT_DRAW_WRITES=0. The base tests now run the
pipeline; agc_driver_pm4_failure_inline and agc_driver_draw_cache_reuse_inline keep the inline path
covered.

Co-Authored-By: Claude <noreply@anthropic.com>

2026-10-15 12:13:26 +02:00

..

debt

fix(libSceAgcDriver): retire a depth surface once another writer covers its memory

2026-10-15 11:00:36 +02:00

ARCHITECTURE.md

perf(agc): pipelined draws and exact draw write ranges on by default

2026-10-15 12:13:26 +02:00

BUILD.md

docs(build): document APS5_TRACE_DRAW_PROGRAMS

2026-10-14 23:39:27 +02:00

CONVENTIONS.md

refactor(docs): separated user and dev in docs + compatibility file

2026-09-28 22:58:17 +03:00

HW_ORACLE.md

feat(shader): follow FP16_OVFL in every f16 result

2026-10-10 04:32:38 -03:00

PROGRESS.md

feat(tools): plot counts in the progress history chart

2026-10-13 11:25:57 +02:00

TechnicalDebt.md

Merge pull request #5511 from JJenkx/perf/spirv-bounded-redundancy

2026-10-15 07:38:13 +13:00