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https://github.com/boykopovar/AnyPS5.git
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milescovielloandClaude Opus 5.5
2265e8b1cd
Forspoken (PPSA03984) has a pixel shader with v_interp_p2_f16 v1, ..., v7 op_sel:[0,0,0,1], and main throws "VOP3 interpolation modifiers are not implemented" one second after start. On GFX10, op_sel[3] of a 16-bit VOP3 result selects the high half of the destination and keeps the other half. The decoder already maps that bit to destination.sdwaSel 5 for the other 16-bit VOP3 ops, and write16Bits/writeRawU32 then insert the result into bits 31:16 and keep bits 15:0. v_interp_p2_f16 is the only 16-bit-result interpolation instruction, so only it accepts the bit; other op_sel bits and the bit on the 32-bit-result p1ll/p1lv forms are still refused. agc_vop3_interp_decode checks the decoded selector with and without the bit, and that v_interp_p1ll_f16 still refuses it. In agc_driver_interpolation_f16 the second v_interp_p2_f16 now writes the high half of a register holding 0x00001234, and the GPU result must keep 0x1234 in the low half. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
126 lines
8.2 KiB
C++
126 lines
8.2 KiB
C++
#include "RdnaDecoder/RdnaInstructionDecoder.hpp"
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#include <cstdint>
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#include <cstdio>
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#include <exception>
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#include <string>
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#include <vector>
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using namespace ShaderRecompiler;
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namespace {
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struct Accepted {
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std::vector<std::uint32_t> words;
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RdnaOpcode op;
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const char* name;
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RdnaOperandKind source0Kind;
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std::uint32_t source0Value;
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std::uint32_t attribute;
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std::uint32_t channel;
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bool absolute;
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bool negate;
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bool clamp;
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std::uint32_t omod;
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};
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struct Refused {
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std::vector<std::uint32_t> words;
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const char* reason;
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const char* name;
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};
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}
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int main() {
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constexpr std::uint32_t Destination = 5;
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const std::vector<Accepted> accepted{
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{{0xd6000005u, 0x02020400u}, RdnaOpcode::VInterpP1F32, "v_interp_p1_f32_e64 v5, v2, attr0.x", RdnaOperandKind::VectorRegister, 2u, 0u, 0u, false, false, false, 0u},
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{{0xd6010005u, 0x02020440u}, RdnaOpcode::VInterpP2F32, "v_interp_p2_f32_e64 v5, v2, attr0.y", RdnaOperandKind::VectorRegister, 2u, 0u, 1u, false, false, false, 0u},
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{{0xd6020005u, 0x02000200u}, RdnaOpcode::VInterpMovF32, "v_interp_mov_f32_e64 v5, p20, attr0.x", RdnaOperandKind::IntegerInlineConstant, 1u, 0u, 0u, false, false, false, 0u},
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{{0xd6000005u, 0x0202041fu}, RdnaOpcode::VInterpP1F32, "v_interp_p1_f32_e64 v5, v2, attr31.x", RdnaOperandKind::VectorRegister, 2u, 31u, 0u, false, false, false, 0u},
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{{0xd6000005u, 0x02020420u}, RdnaOpcode::VInterpP1F32, "v_interp_p1_f32_e64 v5, v2, attr32.x", RdnaOperandKind::VectorRegister, 2u, 32u, 0u, false, false, false, 0u},
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{{0xd6000005u, 0x0203fe00u}, RdnaOpcode::VInterpP1F32, "v_interp_p1_f32_e64 v5, v255, attr0.x", RdnaOperandKind::VectorRegister, 255u, 0u, 0u, false, false, false, 0u},
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{{0xd6000205u, 0x02020400u}, RdnaOpcode::VInterpP1F32, "v_interp_p1_f32_e64 v5, |v2|, attr0.x", RdnaOperandKind::VectorRegister, 2u, 0u, 0u, true, false, false, 0u},
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{{0xd6000005u, 0x42020400u}, RdnaOpcode::VInterpP1F32, "v_interp_p1_f32_e64 v5, -v2, attr0.x", RdnaOperandKind::VectorRegister, 2u, 0u, 0u, false, true, false, 0u},
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{{0xd6008005u, 0x02020400u}, RdnaOpcode::VInterpP1F32, "v_interp_p1_f32_e64 v5, v2, attr0.x clamp", RdnaOperandKind::VectorRegister, 2u, 0u, 0u, false, false, true, 0u},
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{{0xd6000005u, 0x0a020400u}, RdnaOpcode::VInterpP1F32, "v_interp_p1_f32_e64 v5, v2, attr0.x mul:2", RdnaOperandKind::VectorRegister, 2u, 0u, 0u, false, false, false, 1u},
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{{0xd6000005u, 0x12020400u}, RdnaOpcode::VInterpP1F32, "v_interp_p1_f32_e64 v5, v2, attr0.x mul:4", RdnaOperandKind::VectorRegister, 2u, 0u, 0u, false, false, false, 2u},
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{{0xd6000005u, 0x1a020400u}, RdnaOpcode::VInterpP1F32, "v_interp_p1_f32_e64 v5, v2, attr0.x div:2", RdnaOperandKind::VectorRegister, 2u, 0u, 0u, false, false, false, 3u},
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{{0xd6000205u, 0x42020400u}, RdnaOpcode::VInterpP1F32, "v_interp_p1_f32_e64 v5, -|v2|, attr0.x", RdnaOperandKind::VectorRegister, 2u, 0u, 0u, true, true, false, 0u},
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{{0xd6000205u, 0x5a020400u}, RdnaOpcode::VInterpP1F32, "v_interp_p1_f32_e64 v5, -|v2|, attr0.x div:2", RdnaOperandKind::VectorRegister, 2u, 0u, 0u, true, true, false, 3u},
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{{0xd6010005u, 0x42020481u}, RdnaOpcode::VInterpP2F32, "v_interp_p2_f32_e64 v5, -v2, attr1.z", RdnaOperandKind::VectorRegister, 2u, 1u, 2u, false, true, false, 0u},
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{{0xd6018205u, 0x02020400u}, RdnaOpcode::VInterpP2F32, "v_interp_p2_f32_e64 v5, |v2|, attr0.x clamp", RdnaOperandKind::VectorRegister, 2u, 0u, 0u, true, false, true, 0u},
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{{0xd6028005u, 0x02000000u}, RdnaOpcode::VInterpMovF32, "v_interp_mov_f32_e64 v5, p10, attr0.x clamp", RdnaOperandKind::IntegerInlineConstant, 0u, 0u, 0u, false, false, true, 0u},
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{{0xd6020005u, 0x0a000000u}, RdnaOpcode::VInterpMovF32, "v_interp_mov_f32_e64 v5, p10, attr0.x mul:2", RdnaOperandKind::IntegerInlineConstant, 0u, 0u, 0u, false, false, false, 1u},
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};
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const std::vector<Refused> refused{
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{{0xd6000005u, 0x02000400u}, "not a vector register", "v_interp_p1_f32_e64 with a non-VGPR coordinate"},
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{{0xd6020005u, 0x02000600u}, "not an interpolation parameter", "v_interp_mov_f32_e64 with a reserved parameter"},
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{{0xd6000005u, 0x02060400u}, "third source is not the inline constant 0", "v_interp_p1_f32_e64 with a third source other than the inline constant 0"},
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{{0xd6000805u, 0x02020400u}, "modifiers are not implemented", "v_interp_p1_f32_e64 with op_sel"},
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{{0xd6000005u, 0x02020500u}, "modifiers are not implemented", "v_interp_p1_f32_e64 with the packed-half selector"},
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{{0xd6000105u, 0x02020400u}, "modifiers are not implemented", "v_interp_p1_f32_e64 with an absolute source 0"},
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{{0xd6020005u, 0x22000200u}, "modifiers are not implemented", "v_interp_mov_f32_e64 with a negated parameter"},
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{{0xd7424005u, 0x00020201u}, "modifiers are not implemented", "v_interp_p1ll_f16 with the high-half destination selector"},
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};
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int failures = 0;
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for (const auto& test : accepted) {
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auto code = test.words;
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code.push_back(0xbf810000u);
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try {
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const auto decoded = RdnaInstructionDecoder{}.Decode(code);
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if (decoded.instructions.empty()) {
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std::fprintf(stderr, "%s decoded no instruction\n", test.name);
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++failures;
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continue;
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}
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const auto& instruction = decoded.instructions[0];
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const auto source0Value = test.source0Kind == RdnaOperandKind::VectorRegister ? instruction.source0.reg : instruction.source0.value;
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if (instruction.op != test.op || instruction.wordCount != test.words.size() || instruction.family != RdnaInstructionFamily::VOP3 ||
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instruction.destination.kind != RdnaOperandKind::VectorRegister || instruction.destination.reg != Destination ||
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instruction.destination.clamp != test.clamp || instruction.destination.omod != test.omod || instruction.sourceCount != 3u ||
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instruction.source0.kind != test.source0Kind || source0Value != test.source0Value ||
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instruction.source0.absolute != test.absolute || instruction.source0.negate != test.negate ||
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instruction.source1.kind != RdnaOperandKind::IntegerInlineConstant || instruction.source1.value != test.attribute ||
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instruction.source2.kind != RdnaOperandKind::IntegerInlineConstant || instruction.source2.value != test.channel) {
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std::fprintf(stderr, "%s decoded to the wrong opcode or operands\n", test.name);
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++failures;
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}
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} catch (const std::exception& error) {
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std::fprintf(stderr, "%s was refused: %s\n", test.name, error.what());
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++failures;
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}
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}
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for (const auto& test : refused) {
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auto code = test.words;
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code.push_back(0xbf810000u);
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std::string refusal;
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try {
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static_cast<void>(RdnaInstructionDecoder{}.Decode(code));
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} catch (const std::exception& error) {
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refusal = error.what();
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}
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if (refusal.find(test.reason) == std::string::npos) {
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std::fprintf(stderr, "%s was not refused\n", test.name);
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++failures;
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}
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}
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for (const std::uint32_t selector : {0x0u, 0x4000u}) {
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const std::vector<std::uint32_t> code{0xd75a0005u | selector, 0x041e0201u, 0xbf810000u};
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try {
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const auto decoded = RdnaInstructionDecoder{}.Decode(code);
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const auto& instruction = decoded.instructions.at(0);
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const std::uint32_t half = selector != 0u ? 5u : 6u;
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if (instruction.op != RdnaOpcode::VInterpP2F16 || instruction.destination.reg != Destination || instruction.destination.sdwaSel != half ||
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instruction.sourceCount != 4u || instruction.source0.reg != 1u || instruction.source1.value != 1u || instruction.source3.reg != 7u) {
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std::fprintf(stderr, "v_interp_p2_f16 v5, v1, attr1.x, v7%s decoded to the wrong opcode or operands\n", selector != 0u ? " op_sel:[0,0,0,1]" : "");
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++failures;
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}
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} catch (const std::exception& error) {
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std::fprintf(stderr, "v_interp_p2_f16 v5, v1, attr1.x, v7%s was refused: %s\n", selector != 0u ? " op_sel:[0,0,0,1]" : "", error.what());
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++failures;
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}
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}
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return failures == 0 ? 0 : 1;
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}
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