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DecodeShaderStages accepts LS, HS and an NGG passthrough ES, reads the 3-bit VGT_TF_PARAM fields, refuses its other bits but DISTRIBUTION_MODE, and needs HOS levels that keep [1, 63]; 0x286-0x287 join the draw key. Local and domain programs are prepared with their stage group: its headers are merged over one set of defaults, and a local program left unbound by the hull header is prepared at its first draw. The local program ends at its jump into the hull half. TessellationLowering lowers LDS and ring addresses that are affine in the control point and relative index to tessellation interfaces with strides from the code, and refuses accesses outside the patch, per-patch writes from other control points and a modified primitive export. Hull lanes read their own saved exec bit, also of host-subgroup-masked copies; other masks are refused, gl_InvocationID loads as a scalar and factors clamp to 63.