From 081abfff05bbe77130a93cdcdaa74268dcc54bcf Mon Sep 17 00:00:00 2001 From: TheTom Date: Thu, 26 Mar 2026 22:47:53 -0500 Subject: [PATCH] docs: add inline block + named-reg results to scoreboard (10 approaches total) --- docs/decode-speed-hardware-analysis.md | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/docs/decode-speed-hardware-analysis.md b/docs/decode-speed-hardware-analysis.md index 8f70862..0f899dc 100644 --- a/docs/decode-speed-hardware-analysis.md +++ b/docs/decode-speed-hardware-analysis.md @@ -91,9 +91,10 @@ We tested 9 approaches total. The pattern is clear: | 2-pair half2 + ternary | 12.0 | 2 divergent | 4 | Branches hurt | | Select chain (zero LUT) | 11.9 | 0 | 8 | Branches kill | | Bit-arithmetic | 11.6 | 0 | 4+ | ALU too heavy | -| Named-reg + ternary select | 10.3 | 4 uniform | 8 | Worst | +| Named-reg + ternary select | 10.3 | 4 uniform | 8 | Worst — ternary kills | | Main (8-entry LUT) | 10.95 | 8 divergent | 0 | Baseline | -| Non-vec FA (nl=2) | 10.2 | 8 divergent | 0 | Wrong kernel | +| Inline block (FA inner loop) | 13.5 | 4 divergent | 0 | I-cache pressure | +| Non-vec FA (nl=2) | 10.2 | 8 divergent | 0 | Wrong kernel for decode | **Any approach that replaces constant reads with branches loses on M2.** The Apple8 GPU's branch predictor/execution is worse than its constant cache. The 4-mag LUT succeeds because it reduces constant addresses (4 vs 8) WITHOUT adding branches.