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Merge pull request #7912 from Rajkamalcode/fix/agc-storage-writeback
fix(agc): skip storage write-back units that lie in no tiled slice
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@@ -3135,6 +3135,10 @@ std::uint64_t StorageTexture::writeBackWindows(std::span<const ImportSegment> se
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}
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if (runs.empty()) return 0;
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auto windows = sliceWindows(runs);
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// A kept unit can lie outside every window: the tracking grid is flat over the guest range
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// while the slices of a 3D surface taper in depth with the level (HasLayer), so the upper
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// depth slices' higher-level blocks belong to no window. There is no tiled data to retile.
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if (windows.empty()) return 0;
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// The linear rows and the tiled bytes of every window, each at a 256-byte position; the tail
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// levels of a layer retile into one scratch region (their block is shared).
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std::vector<std::uint64_t> linearPositions, scratchPositions;
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@@ -0,0 +1,179 @@
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#include "prx/libSceAgcDriver/Execution/include/GuestMemory.hpp"
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#include "prx/libSceAgcDriver/Execution/include/VulkanDevice.hpp"
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#include "prx/libSceAgcDriver/Graphics/include/GuestTextureResource.hpp"
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#include "prx/libSceAgcDriver/Graphics/include/Texture.hpp"
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#include "prx/libSceAgcDriver/Graphics/include/TextureDetiler.hpp"
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#include "prx/libSceAgcDriver/Graphics/include/TextureTiling.hpp"
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#include "prx/libc/include/GuestAllocations.hpp"
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#include "prx/libc/include/GuestArena.hpp"
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#include "prx/libc/include/GuestWriteWatch.hpp"
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#include "VulkanTestDevice.hpp"
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#ifdef _WIN32
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#ifndef NOMINMAX
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#define NOMINMAX
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#endif
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#include <windows.h>
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#else
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#include <sys/mman.h>
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#endif
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#include <algorithm>
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#include <cstdint>
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#include <cstdio>
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#include <cstring>
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#include <iostream>
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#include <string>
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#include <utility>
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#include <vector>
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namespace {
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using AgcDriver::Graphics::DescribeSurface;
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using AgcDriver::Graphics::GuestTextureResource;
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using AgcDriver::Graphics::Require;
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using AgcDriver::Graphics::StorageTexture;
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using AgcDriver::Graphics::TextureDetiler;
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using AgcDriver::Graphics::TextureDimension;
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using AgcDriver::Graphics::TextureTileMode;
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// A thin 3D surface (SW_64KB_R_X, the branch a volume keeps its depth slices in) whose mip tail
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// starts at level 1: with 16 depth slices, level 1's blocks exist for the first 8 slices only
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// (HasLayer's taper) while the flat 64 KiB unit grid spans all 16. The first 64 KiB unit of every
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// slice past the taper start therefore lies outside every (slice, level) window the write-back
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// retiles through, and slices 0..7 have both their units inside windows.
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constexpr std::uint32_t Width = 128;
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constexpr std::uint32_t Height = 128;
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constexpr std::uint32_t Depth = 16;
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constexpr std::uint32_t MipCount = 5;
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constexpr std::uint32_t Format32Float = 22;
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constexpr std::size_t UnitBytes = 65536;
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constexpr std::uint8_t Sentinel = 0xa5;
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std::uint64_t AddressOf(const void* data) {
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return static_cast<std::uint64_t>(reinterpret_cast<std::uintptr_t>(data));
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}
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std::string Hex(std::uint64_t value) {
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char text[24];
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std::snprintf(text, sizeof(text), "0x%llx", static_cast<unsigned long long>(value));
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return text;
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}
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class GuestBlock {
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public:
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explicit GuestBlock(std::size_t bytes) : bytes(bytes) {
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#ifdef _WIN32
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block = static_cast<std::uint8_t*>(GuestArena::GuestArenaAllocate_nid_postfix(bytes, UnitBytes));
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if (block != nullptr) GuestArena::GuestArenaCommit_nid_postfix(block, bytes, PAGE_READWRITE, bytes);
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#else
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void* mapped = mmap(nullptr, bytes + UnitBytes, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
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if (mapped != MAP_FAILED) {
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const auto begin = reinterpret_cast<std::uintptr_t>(mapped);
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const auto aligned = (begin + UnitBytes - 1) & ~(static_cast<std::uintptr_t>(UnitBytes) - 1);
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if (aligned != begin) munmap(mapped, aligned - begin);
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if (aligned + bytes != begin + bytes + UnitBytes) munmap(reinterpret_cast<void*>(aligned + bytes), begin + bytes + UnitBytes - aligned);
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block = reinterpret_cast<std::uint8_t*>(aligned);
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if (AgcDriver::GuestMemory::WriteWatched()) GuestWriteWatch::GuestWriteWatchRegister_nid_postfix(block, bytes);
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}
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#endif
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Require(block != nullptr, "storage write-back no-window: cannot allocate the guest block");
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GuestAllocations::Mutation().Add(block, bytes, true, true, true);
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}
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~GuestBlock() {
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GuestAllocations::Mutation().Remove(block);
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#ifdef _WIN32
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GuestArena::GuestArenaReset_nid_postfix(block, bytes);
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GuestArena::GuestArenaRelease_nid_postfix(block, bytes);
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#else
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munmap(block, bytes);
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if (AgcDriver::GuestMemory::WriteWatched()) GuestWriteWatch::GuestWriteWatchUnregister_nid_postfix(block, bytes);
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#endif
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}
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GuestBlock(const GuestBlock&) = delete;
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GuestBlock& operator=(const GuestBlock&) = delete;
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std::uint8_t* Data() { return block; }
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private:
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std::uint8_t* block = nullptr;
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std::size_t bytes = 0;
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};
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void Run(AgcDriver::VulkanDevice& device) {
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GuestTextureResource resource{};
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resource.width = Width;
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resource.height = Height;
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resource.depthOrLastArray = Depth - 1u;
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resource.mipCount = MipCount;
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resource.tileMode = TextureTileMode::kR64KBX;
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resource.dimension = TextureDimension::k3D;
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resource.format = Format32Float;
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resource.dstSelX = 4;
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resource.dstSelY = 5;
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resource.dstSelZ = 6;
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resource.dstSelW = 7;
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const auto geometry = DescribeSurface(resource);
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Require(geometry.guestBytes >= Depth * UnitBytes, "storage write-back no-window: the fixture's slices are smaller than a 64 KiB unit");
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GuestBlock block(static_cast<std::size_t>(geometry.guestBytes));
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resource.baseAddress = AddressOf(block.Data());
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Require(resource.baseAddress % UnitBytes == 0, "storage write-back no-window: the guest block is not 64 KiB aligned");
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std::memset(block.Data(), Sentinel, static_cast<std::size_t>(geometry.guestBytes));
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AgcDriver::GuestMemory::CollectWrites(resource.baseAddress, static_cast<std::size_t>(geometry.guestBytes));
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AgcDriver::GuestMemory::BumpCollectEpoch();
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auto context = device.graphicsContext();
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TextureDetiler detiler(context);
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context.detiler = &detiler;
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const auto texture = StorageTexture::Create(context, detiler, resource, 0);
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texture->MarkDirty();
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Require(StorageTexture::FindPending(resource.baseAddress, geometry.guestBytes) != nullptr, "storage write-back no-window: the marked image is not pending");
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// The (slice, level) windows sliceWindows would retile a kept unit through: the mip levels of
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// every depth slice HasLayer keeps, each at its tiled offset in the slice.
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std::vector<std::pair<std::uint64_t, std::uint64_t>> windows;
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for (std::uint32_t layer = 0; layer < geometry.layers; ++layer) {
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for (std::uint32_t level = 0; level < geometry.mips.size(); ++level) {
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if (!geometry.HasLayer(level, layer)) continue;
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const auto begin = resource.baseAddress + geometry.GuestLayerOffset(layer) + geometry.mips[level].tiledOffset;
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windows.emplace_back(begin, begin + geometry.mips[level].tiledSize);
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}
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}
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Require(!windows.empty(), "storage write-back no-window: the fixture has no slice windows");
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// Every 64 KiB unit of the flat tracking grid is stored on its own: a unit inside a window
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// stores through the retiler, one outside every window must store nothing and leave the guest
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// bytes alone instead of sizing the retiler's buffers at zero.
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std::size_t units = 0, outside = 0;
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for (auto begin = resource.baseAddress; begin < resource.baseAddress + geometry.guestBytes; begin += UnitBytes) {
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const auto end = std::min(begin + UnitBytes, resource.baseAddress + geometry.guestBytes);
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const auto bytes = static_cast<std::size_t>(end - begin);
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const bool inWindow = std::any_of(windows.begin(), windows.end(), [&](const std::pair<std::uint64_t, std::uint64_t>& window) { return begin < window.second && window.first < end; });
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Require(StorageTexture::FlushPending(begin, bytes, nullptr, "test"), "storage write-back no-window: the unit at +" + Hex(begin - resource.baseAddress) + " was not listed by its flush");
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device.WaitIdle();
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Require(!StorageTexture::FlushPending(begin, bytes, nullptr, "test"), "storage write-back no-window: the unit at +" + Hex(begin - resource.baseAddress) + " stayed pending after its flush");
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++units;
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if (inWindow) continue;
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++outside;
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const bool untouched = std::all_of(block.Data() + (begin - resource.baseAddress), block.Data() + (end - resource.baseAddress), [](std::uint8_t byte) { return byte == Sentinel; });
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Require(untouched, "storage write-back no-window: the flush of the unit at +" + Hex(begin - resource.baseAddress) + ", which lies outside every slice window, wrote to its guest bytes");
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}
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Require(outside != 0, "storage write-back no-window: the thin volume fixture has no unit outside every slice window");
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Require(!texture->Dirty(), "storage write-back no-window: flushing every unit left the image pending");
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std::printf("storage write-back no-window tests passed (%zu units, %zu outside every window)\n", units, outside);
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}
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}
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int main() {
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try {
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const auto device = OpenVulkanTestDevice();
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if (!device) return VulkanTestSkipped;
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Run(*device);
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return 0;
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} catch (const std::exception& error) {
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std::cerr << error.what() << '\n';
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return 1;
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}
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}
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@@ -154,7 +154,7 @@
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- [Custom MSAA sample locations](../../../core/libs/prx/libSceAgcDriver/Graphics/src/State.cpp) (libSceAgcDriver) support a uniform 1x1 pattern for 2, 4 or 8 samples through VK_EXT_sample_locations. Patterns varying across the guest's 2x2 pixel grid use a 2x2 sample location grid, anchored at the framebuffer origin like the guest's while the window offset is zero, on devices whose `maxSampleLocationGridSize` for the sample count is a multiple of 2x2. On other devices every pixel takes the pattern's pixel (0,0) locations (`PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_*`, its first registers and the corner the grid is anchored at), and the first such pipeline of each sample count logs `[gpu] no 2x2 sample location grid`. The RTX 5070 reports 2x4 for 2 samples, 2x2 for 4 and 1x2 for 8; an AMD Radeon integrated GPU reports 2x2 for each; an RTX 3070 Laptop GPU (driver 617.42) reports 1x1 for every count. With that stand-in the top-left pixel of every 2x2 quad matches the console and the other three use its positions. A pattern that only reorders one set of positions between pixels, as a 2x checkerboard pattern puts its samples at x = +4/16 and -4/16 and swaps them on odd rows, keeps every position and the number of samples a primitive covers in each pixel, so a resolve that averages a pixel's samples, or takes their minimum or maximum, sees the console's values. Sample i of an odd row then holds what the console stores in sample 1 - i: a pass that reads the samples by index, as checkerboard reconstruction does, exchanges the two half-pixels of odd rows, which can show as combing along vertical edges, and per-sample shading, sample-mask exports and coverage inputs see the swapped indices too. A pattern whose pixels hold different positions draws pixel (0,0)'s positions in each pixel whose own differ. A device's pipelines and render pass begins take the same stand-in for a given pattern, so a sample-location-compatible depth image is not drawn with one set of locations and transitioned or tested with another. A multisampled rasterizer drawing into one-sample color targets, and a one-sample depth target if any, with MSAA_ENABLE set, no alpha-to-coverage and no coverage pixel input is drawn with one sample at sample 0's location in each pixel of the grid, as the targets keep only sample 0's coverage. Without PS_ITER_SAMPLE such a draw also refuses centroid inputs, and keeps PERSP_SAMPLE, LINEAR_SAMPLE and ANCILLARY: a pixel shaded once is taken to get sample 0's barycentrics and sample index 0. With PS_ITER_SAMPLE only sample 0's invocation reaches the targets, so its sample and centroid barycentrics are taken to be sample 0's and the draw is shaded once. Both are inferred, not measured. The pixel shader runs once per pixel with sample number 0, so ANCILLARY reads sample 0 and POS_X_FLOAT and POS_Y_FLOAT keep the position `SPI_BARYC_CNTL` names. PERSP_CENTER and LINEAR_CENTER inputs on this path are interpolated at sample 0's location on the host, where the console uses the pixel center; one-sample depth images are created with `SAMPLE_LOCATIONS_COMPATIBLE_DEPTH` when the device supports it, as multisampled ones already were; this is how VK_AMD_mixed_attachment_samples defines the case, and it is not measured on PS5 hardware. Other mixed sample counts throw. Devices without the required sample count, four subpixel bits or the full guest coordinate range refuse custom patterns. Depth images remain in GENERAL between draws, and render passes cannot continue across pattern changes. Guest offsets retain the existing decoder's signed four-bit, sixteenth-pixel interpretation; PS5 coverage and interpolation equivalence have not been measured on hardware.
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- [Single-sample scan into a multisampled depth target](../../../core/libs/prx/libSceAgcDriver/Graphics/src/State.cpp) (libSceAgcDriver) - a draw with `PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES` = 0 and `PA_SC_MODE_CNTL_0.MSAA_ENABLE` clear into a multisampled depth target rasterizes the depth target's sample count with every sample at the pixel center, as a single-sample scan into a multisampled color target already does. radeonsi programs this `MSAA_ENABLE` and `PA_SC_AA_CONFIG` with the depth buffer's own sample count when GL multisampling is disabled on a multisampled framebuffer ([L1066-L1068](https://github.com/openbsd/xenocara/blob/1b39033df8d928ec247ca64448c4a63c72302db7/lib/mesa/src/gallium/drivers/radeonsi/si_state.c#L1066-L1068), [L3485-L3512](https://github.com/openbsd/xenocara/blob/1b39033df8d928ec247ca64448c4a63c72302db7/lib/mesa/src/gallium/drivers/radeonsi/si_state.c#L3485-L3512)), although its comment lists Z samples as at most the coverage samples ([L3439](https://github.com/openbsd/xenocara/blob/1b39033df8d928ec247ca64448c4a63c72302db7/lib/mesa/src/gallium/drivers/radeonsi/si_state.c#L3439)) and it sets `DB_EQAA.MAX_ANCHOR_SAMPLES` to the Z sample count, where PPSA18216 sets `DB_EQAA` to 0. GL then lets every sample take the single-sample depth ([L185-L190](https://github.com/KhronosGroup/OpenGL-Registry/blob/6af574a14089ccfee87efe230ebcdd8742859813/extensions/ARB/ARB_multisample.txt#L185-L190)) and the fragment be treated as in multisampling with full coverage ([L422-L425](https://github.com/KhronosGroup/OpenGL-Registry/blob/6af574a14089ccfee87efe230ebcdd8742859813/extensions/ARB/ARB_multisample.txt#L422-L425)), which is what this draws: each depth and stencil sample is tested and written with the depth at the pixel center. GL also lets an implementation test only a centermost sample and set every sample from it ([L425-L434](https://github.com/KhronosGroup/OpenGL-Registry/blob/6af574a14089ccfee87efe230ebcdd8742859813/extensions/ARB/ARB_multisample.txt#L425-L434)), which differs when a pixel's stored samples differ; which one the console does, whether it instead evaluates the depth plane at each sample position, and how its occlusion queries count such a draw, is not measured on hardware. Points, lines, alpha-to-coverage, `DB_EQAA` Z interpolation or overrasterization, a pixel program reading the sample index, a sample-mask export and a single-sample color target next to the multisampled depth target throw
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- [DCC display buffers](../../../core/libs/prx/libSceAgcDriver/Execution/src/VulkanDevice.cpp) are presented only when all keys of the console's DCC extent agree on uncompressed or a fast-clear code, padding keys included; other keys, and register-clear keys over a pending image, throw.
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- [Storage image write-back](../../../core/libs/prx/libSceAgcDriver/Graphics/src/Texture.cpp) (libSceAgcDriver) stores the GPU results over a CPU-stamped range whose guest bytes equal the copy taken when the image's layers got their generation (images up to 1 MiB whose guest bytes were settled at that point, with no unit shadow, pending image results or recorded GPU store over them; other images keep the previous rule: the CPU's bytes win). A CPU store that rewrites the baseline value after the GPU changed it is not told apart from no store, and the GPU result wins there. The 1 MiB limit is a choice, not a console value. A range a queued draw commit still has to read is left pending whatever the stamps say ([`DrawPipeline::HeldReads`](../../../core/libs/prx/libSceAgcDriver/Execution/include/Driver/Draw/DrawPipeline.hpp)), so a title that recycles one allocation between an index buffer and a storage image sees the draw's own indices; the trade is a title that reads a surface as index data and means the image gets the pre-image bytes instead, since the reservation does not compare the command-stream positions of the draw and of the image's write. `APS5_NO_QUEUED_DRAW_READ_ORDER=1` restores the old behaviour, and the `[storage]` line counts the listings the hold turned away (`held for a queued draw read`) and the `[draw] pipelined` line the stores it held. The hold covers what the commit reads of guest memory: the index range, the vertex input ranges as their descriptor extents ([`QueuedDrawReadRanges`](../../../core/libs/prx/libSceAgcDriver/Execution/src/Driver/Memory/WrittenBuffers.cpp), since the bytes a draw fetches depend on the highest index, which only the commit knows) and the source of a queued DMA copy. Every other commit-time read goes through the flush hook, so it sees the bytes the hold protects. Two commit-time reads are outside the hold: the texels a register or cmask clear materialization reads from the draw's own colour target (through the hook, so ordered, but the hold does not cover a render target), and a CPU read whose store the hold turned away, which sees the pre-image bytes. Nothing retries a refused store: the image reaches guest memory with the next flush of that range (the queue worker's idle store, a `WAIT_REG_MEM` poll over it, a later read or write of it).
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- [Storage image write-back](../../../core/libs/prx/libSceAgcDriver/Graphics/src/Texture.cpp) (libSceAgcDriver) stores the GPU results over a CPU-stamped range whose guest bytes equal the copy taken when the image's layers got their generation (images up to 1 MiB whose guest bytes were settled at that point, with no unit shadow, pending image results or recorded GPU store over them; other images keep the previous rule: the CPU's bytes win). A CPU store that rewrites the baseline value after the GPU changed it is not told apart from no store, and the GPU result wins there. The 1 MiB limit is a choice, not a console value. A range a queued draw commit still has to read is left pending whatever the stamps say ([`DrawPipeline::HeldReads`](../../../core/libs/prx/libSceAgcDriver/Execution/include/Driver/Draw/DrawPipeline.hpp)), so a title that recycles one allocation between an index buffer and a storage image sees the draw's own indices; the trade is a title that reads a surface as index data and means the image gets the pre-image bytes instead, since the reservation does not compare the command-stream positions of the draw and of the image's write. `APS5_NO_QUEUED_DRAW_READ_ORDER=1` restores the old behaviour, and the `[storage]` line counts the listings the hold turned away (`held for a queued draw read`) and the `[draw] pipelined` line the stores it held. The hold covers what the commit reads of guest memory: the index range, the vertex input ranges as their descriptor extents ([`QueuedDrawReadRanges`](../../../core/libs/prx/libSceAgcDriver/Execution/src/Driver/Memory/WrittenBuffers.cpp), since the bytes a draw fetches depend on the highest index, which only the commit knows) and the source of a queued DMA copy. Every other commit-time read goes through the flush hook, so it sees the bytes the hold protects. Two commit-time reads are outside the hold: the texels a register or cmask clear materialization reads from the draw's own colour target (through the hook, so ordered, but the hold does not cover a render target), and a CPU read whose store the hold turned away, which sees the pre-image bytes. Nothing retries a refused store: the image reaches guest memory with the next flush of that range (the queue worker's idle store, a `WAIT_REG_MEM` poll over it, a later read or write of it). A kept 64 KiB unit that lies outside every (slice, level) window stores nothing: the tracking grid is flat over the guest range while 3D slices taper in depth with the mip level (`HasLayer`), so the higher depth slices' higher-level blocks belong to no window. The console's tracking of such units is not measured.
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- [16-bit float display buffers](../../../core/libs/prx/libSceAgcDriver/Execution/src/DisplayBuffer.cpp) (libSceAgcDriver, libSceVideoOut) - pixel formats `0xC001000622000000` and `0xC001000600000000` are taken as R16G16B16A16 and B16G16R16A16 float, eight bytes per texel, as [KytyPS5](https://github.com/KytyPS5/KytyPS5/blob/59183dbfa81ed7efdff6069177fed50de0552725/src/graphics/host_gpu/renderer/image/imageInfo.h) maps them and [SharpProspero](https://github.com/SvenGDK/SharpProspero/blob/5dfdb4b0b166e83dc9ae275001afb695f12c7174/src/SharpProspero/Interop/VideoOut/VideoOutTypes.cs) names them (`Rgba16Float`, `Bgra16Float`); PPSA11386 registers 3840x2160 tiled buffers of the first. The tiled layout is assumed to be the 8-byte SW_64KB_R_X equation of `TextureSwizzleEquations.hpp` applied to full coordinates, as addrlib applies it, by analogy with the 32-bit scanout; `ColorTargetLayout` applies the equations to in-block coordinates, which for 8-byte texels differs in every odd 64-row block row (address bit 11 takes y bit 6) and for 16-byte texels also differs, so a float display buffer written through `WriteColorTarget` and presented from guest memory would show those rows misplaced. The values are assumed to be linear light and are encoded with the sRGB curve for the 8-bit output. Bits 32-39 of these formats are `0x06`, as in the 10-bit formats SharpProspero lists without sRGB transfer, while its sRGB formats have `0x00`, its 10-bit PQ formats `0x04` (with `0x07` in bits 40-47) and its float BT.2100 PQ formats `0x07`: they show only that these formats are not the sRGB ones. NaN and negative values give 0, values of 1 and above give 255, alpha is linear. Neither the layout nor the transfer is verified against console or title frames, and HDR output is not modelled. DCC metadata on a float buffer throws.
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- [BT.2100 PQ display buffers](../../../core/libs/prx/libSceAgcDriver/Execution/include/PqToSdr.hpp) (libSceAgcDriver, libSceVideoOut) - pixel formats `0x8100070422000000` and `0x8100070400000000` are taken as 10:10:10:2 texels with BT.2020 primaries and the SMPTE ST 2084 transfer, red or blue in the low bits, as [SharpProspero](https://github.com/SvenGDK/SharpProspero/blob/5dfdb4b0b166e83dc9ae275001afb695f12c7174/src/SharpProspero/Interop/VideoOut/VideoOutTypes.cs) names them (`Rgb10A2Bt2100Pq`, `Bgr10A2Bt2100Pq`) and [KytyPS5](https://github.com/KytyPS5/KytyPS5/blob/59183dbfa81ed7efdff6069177fed50de0552725/src/graphics/host_gpu/renderer/image/imageInfo.h) maps the first; PPSA01317 registers display buffers of the first when its output reports HDR. With HDR output they are presented unchanged through an HDR10 swapchain (`VK_COLOR_SPACE_HDR10_ST2084_EXT`, 10-bit, with `VK_EXT_hdr_metadata`); otherwise they are converted to 8-bit sRGB: ST 2084 EOTF, BT.2020 to BT.709 primaries with negative components clipped, a luminance tone map and the sRGB encoding. The tone map is ours: min(203 nits, white level) is SDR white (the BT.2408 HDR reference white), luminance passes unchanged up to 0.75 of it and an extended Reinhard shoulder above reaches 1.0 at the white level, the peak sceSystemServiceGetHdrToneMapLuminance last reported to the title (or the current one when it never asked), since titles read it once. How a console shows such a buffer on an SDR display is unknown. Alpha is opaque.
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- [HDR output override](../../../core/libs/prx/libSceAgcDriver/Execution/src/HostHdr.cpp) - setting `APS5_FORCE_SDR` suppresses HDR availability reported to titles while retaining the detected display and surface capabilities. It selects the existing SDR presentation path; it does not add support for floating-point BT.2100 PQ buffers (`0xC001070722000000` and `0xC001070700000000`), whose presentation remains refused. The override does not change the host display settings.
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