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m2 (AI Agent)andClaude Opus 5.5
d83f541c54
Every OpGroupNonUniformBallot now goes through SpirvModule::AddSubgroupBallot. A repeated ballot of the same predicate in the same block becomes an OpCopyObject of the first ballot. Within one block the active invocations do not change, so the result is identical. The cache is cleared at every label, function boundary, function call and demote, and helper functions keep their own cache. When SPIRV-Tools is enabled, block merging and specialization can still put two ballots of one predicate into the same block after emission, so ValidateAndOptimizeSpirv collapses repeated block ballots the same way on every module it returns, optimized or not. NVIDIA 580's SPIR-V compiler segfaulted (libnvidia-gpucomp+0xe3facc) on GTA V compute shaders that ballot one predicate many times in a block. One such shader had 163 repeated ballots across three blocks. With them collapsed, both crashing captures (compute-fe506552cec99bfc and compute-c02e5e3f35010fa5) compile. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
203 lines
9.4 KiB
C++
203 lines
9.4 KiB
C++
#include "SpirvBackend/SpirvEmitter.hpp"
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#include "SpirvBackend/SpirvEmitterInstructions.hpp"
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#include "SpirvBackend/SpirvMemory/SpirvSubgroup.hpp"
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#include "SpirvBackend/SpirvMemory/SpirvConstants.hpp"
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#include <array>
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#include <bit>
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#include <cstdio>
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#include <stdexcept>
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#include <span>
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#include <string>
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#include <unordered_map>
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#include <utility>
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#include <vector>
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using namespace ShaderRecompiler;
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namespace {
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using Value = std::array<std::uint32_t, 4>;
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using Lanes = std::vector<Value>;
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void Require(bool condition, const char* reason) {
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if (!condition) throw std::runtime_error(reason);
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}
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class Subgroup {
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public:
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explicit Subgroup(std::uint32_t size) : size(size) {}
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void Set(std::uint32_t id, Lanes lanes) {
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values[id] = std::move(lanes);
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}
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const Lanes& Get(std::uint32_t id) const {
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return values.at(id);
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}
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void Execute(std::span<const std::uint32_t> code) {
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for (std::size_t offset = 5; offset < code.size();) {
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const auto count = code[offset] >> 16u;
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Require(count != 0 && count <= code.size() - offset, "malformed SPIR-V instruction");
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const auto words = code.subspan(offset, count);
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const auto op = static_cast<spv::Op>(words[0] & 0xffffu);
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offset += count;
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switch (op) {
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case spv::OpTypeInt:
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case spv::OpTypeBool:
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case spv::OpTypeVector:
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continue;
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case spv::OpStore:
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values[words[1]] = values.at(words[2]);
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continue;
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default:
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break;
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}
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auto& result = values[words[2]];
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result.resize(size);
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for (std::uint32_t lane = 0; lane < size; ++lane) {
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const auto arg = [&](std::size_t index) -> const Value& { return values.at(words[index]).at(lane); };
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auto& value = result[lane];
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switch (op) {
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case spv::OpConstant: value[0] = words[3]; break;
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case spv::OpConstantTrue: value[0] = 1; break;
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case spv::OpConstantFalse: value[0] = 0; break;
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case spv::OpLoad: value = arg(3); break;
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case spv::OpCopyObject: value = arg(3); break;
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case spv::OpBitwiseAnd: value[0] = arg(3)[0] & arg(4)[0]; break;
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case spv::OpBitwiseOr: value[0] = arg(3)[0] | arg(4)[0]; break;
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case spv::OpBitwiseXor: value[0] = arg(3)[0] ^ arg(4)[0]; break;
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case spv::OpIAdd: value[0] = arg(3)[0] + arg(4)[0]; break;
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case spv::OpIMul: value[0] = arg(3)[0] * arg(4)[0]; break;
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case spv::OpShiftRightLogical: value[0] = arg(3)[0] >> arg(4)[0]; break;
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case spv::OpShiftLeftLogical: value[0] = arg(3)[0] << arg(4)[0]; break;
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case spv::OpINotEqual: value[0] = arg(3)[0] != arg(4)[0]; break;
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case spv::OpIEqual: value[0] = arg(3)[0] == arg(4)[0]; break;
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case spv::OpULessThan: value[0] = arg(3)[0] < arg(4)[0]; break;
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case spv::OpLogicalAnd: value[0] = arg(3)[0] && arg(4)[0]; break;
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case spv::OpSelect: value = arg(3)[0] ? arg(4) : arg(5); break;
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case spv::OpCompositeExtract: value[0] = arg(3).at(words[4]); break;
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case spv::OpVectorExtractDynamic: value[0] = arg(3).at(arg(4)[0]); break;
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case spv::OpCompositeConstruct:
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for (std::size_t component = 0; component < count - 3u; ++component) value.at(component) = arg(3u + component)[0];
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break;
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case spv::OpGroupNonUniformBallot:
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value.fill(0);
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for (std::uint32_t source = 0; source < size; ++source) {
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if (values.at(words[4])[source][0]) value[source / 32u] |= 1u << (source % 32u);
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}
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break;
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case spv::OpGroupNonUniformBallotFindLSB:
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value[0] = 0xffffffffu;
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for (std::uint32_t component = 0; component < 4; ++component) {
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if (arg(4)[component] != 0) {
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value[0] = component * 32u + std::countr_zero(arg(4)[component]);
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break;
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}
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}
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break;
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case spv::OpGroupNonUniformShuffle:
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Require(arg(5)[0] < size, "shuffle escaped the host subgroup");
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value = values.at(words[4]).at(arg(5)[0]);
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break;
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default:
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throw std::runtime_error("unexpected opcode in subgroup test: " + std::to_string(op));
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}
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}
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}
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}
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private:
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std::uint32_t size;
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std::unordered_map<std::uint32_t, Lanes> values;
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};
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void Check(std::uint32_t size, const Value& masks) {
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IrProgram program;
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program.SetWaveSize(32);
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SpirvEmitterState state(program, {});
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state.splitSubgroup = size > 32;
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state.subgroupLocalInvocationIdVariable = state.module.AllocateId();
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SpirvValueEmitContext context(state);
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context.scratchU32Variable = state.module.AllocateId();
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IrValue source(IrOpcode::GetAttribute, IrType::U32, 1);
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IrValue predicate(IrOpcode::GetExec, IrType::Bool, 2);
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IrValue requestedLane(IrOpcode::GetAttribute, IrType::U32, 3);
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IrValue first(IrOpcode::ReadFirstLane, IrType::U32, 4);
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first.AddArgument(&source);
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first.AddArgument(&predicate);
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IrValue read(IrOpcode::ReadLane, IrType::U32, 5);
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read.AddArgument(&source);
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read.AddArgument(&requestedLane);
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IrValue control(IrOpcode::Void, IrType::U32, 6);
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control.SetImmediateU32(0x7c1fu);
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IrValue swizzle(IrOpcode::SwizzleU32, IrType::U32, 7);
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swizzle.AddArgument(&source);
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swizzle.AddArgument(&control);
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swizzle.AddArgument(&predicate);
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IrValue replacement(IrOpcode::Void, IrType::U32, 8);
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replacement.SetImmediateU32(0x12345678u);
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IrValue writeTarget(IrOpcode::Void, IrType::U32, 9);
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writeTarget.SetImmediateU32(7u);
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IrValue write(IrOpcode::WriteLane, IrType::U32, 10);
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write.AddArgument(&replacement);
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write.AddArgument(&writeTarget);
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write.AddArgument(&source);
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const auto sourceId = context.Def(&source);
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const auto predicateId = context.Def(&predicate);
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const auto requestedId = context.Def(&requestedLane);
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const auto logicalId = EmitSubgroupLocalInvocationId(state);
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const auto ballot = context.Ballot(&predicate);
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const auto readFirst = EmitReadFirstLane(context, first);
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const auto readLane = EmitReadLane(context, read);
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const auto active = EmitBallotLaneActiveBool(state, ballot, requestedId);
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const auto quad = EmitDppGroupPermTargetLane(state, logicalId, 0x1bu, 2u);
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const auto quadValue = context.Shuffle(read, 0, quad.lane);
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const auto hardwareActive = EmitSubgroupLaneActiveBool(state, requestedId);
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const auto swizzled = EmitSwizzleU32(context, swizzle);
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const auto written = EmitWriteLane(context, write);
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Subgroup subgroup(size);
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Lanes host(size), sources(size), predicates(size), requested(size);
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for (std::uint32_t lane = 0; lane < size; ++lane) {
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host[lane][0] = lane;
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sources[lane][0] = 0x1000u + lane;
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predicates[lane][0] = (masks[lane / 32u] >> (lane % 32u)) & 1u;
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requested[lane][0] = 31u - lane % 32u;
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}
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subgroup.Set(state.subgroupLocalInvocationIdVariable, host);
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subgroup.Set(sourceId, sources);
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subgroup.Set(predicateId, predicates);
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subgroup.Set(requestedId, requested);
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subgroup.Execute(state.module.Finalize());
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for (std::uint32_t lane = 0; lane < size; ++lane) {
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const auto mask = masks[lane / 32u];
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const auto base = lane / 32u * 32u;
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Require(subgroup.Get(logicalId)[lane][0] == lane % 32u, "lane id escaped its wave32");
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Require(subgroup.Get(ballot)[lane] == Value{mask, 0, 0, 0}, "ballot mixed independent wave32s");
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Require(subgroup.Get(readFirst)[lane][0] == 0x1000u + base + (mask == 0 ? 0u : std::countr_zero(mask)), "readfirstlane read a different wave32");
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Require(subgroup.Get(readLane)[lane][0] == 0x1000u + base + requested[lane][0], "readlane read a different wave32");
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Require(subgroup.Get(active)[lane][0] == ((mask >> requested[lane][0]) & 1u), "source lane activity came from another wave32");
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Require(subgroup.Get(quadValue)[lane][0] == 0x1000u + (lane & ~3u) + 3u - lane % 4u, "DPP quad permutation crossed waves");
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Require(subgroup.Get(hardwareActive)[lane][0] == 1u, "upper wave32 lanes were treated as inactive");
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Require(subgroup.Get(swizzled)[lane][0] == (((mask >> requested[lane][0]) & 1u) != 0 ? 0x1000u + base + requested[lane][0] : 0u), "DS swizzle read another wave32 or ignored source EXEC");
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Require(subgroup.Get(written)[lane][0] == (lane % 32u == 7u ? 0x12345678u : 0x1000u + lane), "writelane missed the upper wave32");
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}
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}
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}
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int main() {
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try {
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for (std::uint32_t size : {32u, 64u, 128u}) {
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for (const Value& masks : {Value{0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu}, Value{1, 0x80000000u, 0x100, 0x4000}, Value{0x55555555u, 0xaaaaaaaau, 0x12345678u, 0xfedcba98u}, Value{0, 1, 0, 0x80000000u}, Value{1, 0, 0x80000000u, 0}, Value{0, 0, 0, 0}}) {
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Check(size, masks);
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}
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}
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std::puts("wave32 wide subgroup tests passed");
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return 0;
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} catch (const std::exception& error) {
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std::fprintf(stderr, "%s\n", error.what());
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return 1;
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}
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}
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